1. Field of the Invention
The present invention relates to a system, a method, and a program for detecting a defect of a semiconductor during semiconductor manufacturing process.
2. Related Art
An electron microscope typified by a scanning electron microscope (SEM) is now essential as a semiconductor process evaluation tool. Actually, however, the electron microscope has a limited inspection field of view because of its high magnification as compared with an optical microscope, and it still takes lots of time and labor for the electron microscope to inspect an entire surface of a wafer. Due to these, it is conventionally general to perform optical defect detection, extract a portion to be inspected, at high speed from data on a position and a magnitude of a defect on the surface of the wafer, and then observe a shape of the defect extracted by the optical defect detection using the electron microscope. Nevertheless, it is unclear how the defect differs in shape from a semiconductor pattern design only by recognizing the shape, the magnitude, the position and the like of the defect.
To solve the disadvantage, there is proposed a method for classifying a defect by superimposing a defect image acquired by the electron microscope on a pattern profile based on layout design data on a semiconductor pattern using CAD (Computer Aided Design) (hereinafter, “CAD data”), and by comparing the CAD data with the shape of the defect image (see Japanese Patent Application Laid-Open No. 2000-294611).
Generally, in the optical defect detection, a portion having a different shape is extracted by comparison of an image acquired for every chip (die) on a wafer with an image acquired from another chip. Since the extracted portion differs in shape from that on another chip, the extracted portion highly likely includes a defect, e.g., adhesion of a contamination onto the wafer, occurring randomly (hereinafter, “random defect”) in a semiconductor manufacturing process. The optical proximity effect (OPE) has a yearly increasing severe influence on formation of a semiconductor pattern, with the refinement of the semiconductor pattern. Due to this, a defect resulting from a pattern layout, a shape of a mask pattern by optical proximity correction (OPC), or an operating state, an operating condition or the like of an exposure device tends to occur. Differently from the random defect, such a defect (hereinafter, “systematic defect”) is difficult to detect by the optical detection because the systematic defect equally occurs to each chip.
At present, therefore, a shape of a pattern to be formed on a wafer after exposure under planned conditions is simulated based on design data, exposure condition and the like of a mask pattern that has been subjected to an OPC processing. A portion in which a shape difference exceeds a pre-considered standard is detected as an OPC risky region by comparing the resulted shape of the pattern from simulation with CAD data, thereby detecting a portion having a greater risk of occurrence of a systematic defect.
However, a circuit structure of a semiconductor is more complicated as recent high integration progresses rapidly. In some cases, a portion that appears to have no adhesion of a contamination and to be finished into a shape close to that of the CAD data causes a malfunction. Such a defect often occurs to, for example, a fine and thin portion in which quite high accuracy is required for signal transmission rate and circuit operation timing during actual operation. It is difficult to extract the defect occurring depending on a finishing accuracy required for circuit operation, by the above-stated method for detecting a defect only based on the shape.